Electronic Noise Analysis of Source-Engineered Phosphorene/Si Heterojunction Dopingless Tunnel-FET

The implementation of two-dimensional layered material in the source-region of a Si-based tunnel field-effect transistors (T-FETs) offers some remarkable properties viz. ultralow power utilizations. Simultaneously, it becomes imperative to study the noise characteristics of the device so as to get successful execution at circuit level. The present simulation-based study is dedicated to investigate and analyse the frequency response of the device against noise in various conditions. Minimum noise figure, noise conductance, gate and drain autocorrelation and crosscorrelation are some parameters, which are plotted against gate-to-source voltages for the device channel lengths 45 nm, 32 nm, 22 nm and 14 nm. The numerical simulation as validation tool is carried out on ATLAS (TM), a two dimensional device simulator from Silvaco.