Accelerating Graph Neural Networks in Pytorch with HLS and Deep Dataflows

Graph neural networks (GNNs) combine sparse and dense data compute requirements that are challenging to meet in resource-constrained embedded hardware. In this paper, we investigate a dataflow of dataflows architecture that optimizes data access and processing element utilization. The architecture is described with high-level synthesis and offers multiple configuration options including varying the number of independent hardware threads, the interface data width and the number of compute units per thread. Each hardware thread uses a fine-grained dataflow to stream words with a bit-width that depends on the network precision while a coarse-grained dataflow links the thread stages streaming partially-computed matrix tiles. The accelerator is mapped to the programmable logic of a Zynq Ultrascale device whose processing system runs Pytorch extended with PYNQ overlays. Results based on the citation networks show a performance gain of up to 140x with multi-threaded hardware configurations compared with the optimized software implementation available in Pytorch. The results also show competitive performance of the embedded hardware compared with other high-performance state-of-the-art hardware accelerators.