Scalable Detection of Hardware Trojans Using ATPG-Based Activation of Rare Events

Semiconductor supply chain vulnerability is a major concern in designing trustworthy systems. Malicious implants, popularly known as hardware Trojans (HTs), can get introduced at different stages in the system-on-chip (SoC) design cycle. While there are promising test generation techniques for HT detection, they have two practical limitations: 1) these approaches are designed to activate rare states while ignoring rare transitions and 2) these approaches are not scalable for large designs. In this article, we propose a scalable test generation framework to address the above challenges. Our threat model assumes that an adversary may exploit rare events consisting of rare signals (states) as well as rare branches (transitions). We show that the rare branch coverage problem can be mapped to the rare signal coverage problem. We propose a scalable framework for detecting HTs using automated test pattern generation (ATPG)-based activation of rare events. Specifically, we utilize the complementary abilities of N-detection and maximal clique activation of rare events to generate efficient test patterns. Experimental evaluation shows that our ATPG-based framework is scalable and significantly outperforms the state-of-the-art test generation-based Trojan detection techniques.