A Wide-Range ISFET Readout Circuit with Low-Power Linearity Enhancement

被引：0
|
作者：
Chen, Kaichang [1 ]
Tripathi, Prateek [1 ,2 ]
Moser, Nicolas [1 ,2 ]
Georgiou, Pantelis [1 ,2 ]
机构：
[1] Imperial Coll London, Dept Elect & Elect Engn, London SW7 2BT, England
[2] Imperial Coll London, Inst Biomed Engn, Ctr Bioinspired Technol, London SW7 2AZ, England
来源：
2023 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, ISCAS | 2023年
关键词：
ISFET; translinear circuits; CCO-based ADC; linearity; wide input range; chemical readout; CMOS;
D O I：
10.1109/ISCAS46773.2023.10181433
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
This work presents a chemical readout system designed in TSMC 180nm technology. The proposed design has an input range of 0-1.8V, linearity (R-2) of over 0.997, high sensitivity of 600 KHz/pH, a maximum frame rate of 1.4 mu s and a small chip area. The readout system includes an Ion-Sensitive Field Effect Transistor (ISFET) front-end that works in the saturation region, trans-linear circuits for linearity enhancement, and a CCO (Current Controlled Oscillator)-based ADC as an analogue to digital converter. This system was designed to provide a good balance between input range, linearity, and silicon area. The proposed architecture is capable of compensating for 400mV of trapped charge by changing the biasing current of the lineariser as a universal quadratic equation solver.
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页数：5
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