Analog Implementation of Neural Network

As Moore's law comes to the end, to increase the speed and density of computation, analog based approach has to be revisited. The multiplication and addition operations can be easily done by digital circuits but the power consumption and area occupied by processing units will drastically increase. The implementation of the same operations performed by analog circuits not only provides continuous interrupt-free operations but also reduces area and power consumption considerably. This makes analog circuit implementation ideal for Neural networks (NN) processing. In this work, the single neuron has been realized by a Common Drain amplifier, Trans-Impedance Amplifier(TIA) and CMOS rectifier circuits. The 3 x 1 NN(3 input x 1 output), 3 x 3 NN, and two layers of 3 x 3 NN have been implemented using this single neuron and only forward propagation has been performed. The simulation has been done on LTSpice for 16 nm CMOS Technology and results have been compared with theoretical values. The implemented two-layer 3 x3 NN is capable to work up to 61MHz and found a 90% reduction in transistor count compared to the 8-bit Vedic multiplier NN.