A differential block and NCG cell based four stage CMOS amplifier

In this paper, a four stage CMOS operational amplifier is proposed to drive a large capacitive load of 500 pF. The designed operational amplifier shows high stability besides meeting intended specifications like high gain, good swing etc. It is already known that the number of high impedance nodes increases as number of stages in amplifier increases so design of frequency compensation network for a four stage amplifier has been a quite challenging work. The designed compensation network exploited in this work is unique and is the combination of negative capacitance generator (NCG) cell and a differential block along with a compensation capacitor. The NCG cell's incorporation has lowered preceding stage's parasitic capacitance resulting in to improvement in GBW significantly and use of differential block in feedback path has resulted into reduction of compensation capacitor's value. The substantiality of the proposed design is verified with help of a number of simulations and theoretical analysis. Simulation results are found in good agreement with the theoretical description. The im-plemented amplifier shows 156 dB, 86.68o and 35.82 M hz as DC gain, phase margin (PM) and Gain Bandwidth (GBW); respectively. The Large signal time response reveals that the proposed circuit settles for its maximum value within 475 ns with 5 % settling error. All simulations have been carried out using 0.18 mu m CMOS tech-nology parameters in Cadence Virtuoso simulator. The supply voltage is set to 1.8 V while power consumption is 1.67 mW.