Simulating Wrong-Path Instructions in Decoupled Functional-First Simulation

被引:0
|
作者
Eyerman, Stijn [1 ]
Van den Steen, Sam [1 ]
Heirman, Wim [1 ]
Hur, Ibrahim [1 ]
机构
[1] Intel Corp, Santa Clara, CA 95051 USA
关键词
MEMORY REFERENCES; FULL-SYSTEM; IMPACT; CPU;
D O I
10.1109/ISPASS57527.2023.00021
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Wrong-path speculative execution on an out-of-order processor core has no impact on an application's functionality and correctness, but it can impact performance by changing the state of caches and predictors. Not modeling wrong-path execution in performance simulation leads to performance projection errors up to 22% for our setup. However, wrong-path execution is challenging to model for common functional-first simulators, because the functional simulator is not aware of branch predictor misses and only provides correct-path instructions. We propose and evaluate multiple wrong-path modeling techniques for functional-first simulators, each with a different accuracy versus simulation speed balance. The novel instruction reconstruction with convergence exploitation technique proves to be the best balanced technique, with about 3x lower error than no wrong path modeling and about 2 to 3x faster simulation than full wrong path emulation.
引用
收藏
页码:124 / 133
页数:10
相关论文
共 1 条
  • [1] Deterministic Clock Gating to Eliminate Wasteful Activity due to Wrong-path Instructions in Out-of-Order Superscalar Processors
    Mohyuddin, Nasir
    Patel, Kimish
    Pedram, Massoud
    2009 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN, 2009, : 166 - 172