Survey on Exact Logic Synthesis Based on Boolean SATisfiability br

Logic synthesis is a critical step in the Electronic Design Automation(EDA). Traditional globalheuristic-based logic synthesis has many challenges as computing power keeps increasing and new computingparadigms emerge. There is a problem with heuristic algorithm in a suboptimal solution. As computing powerimproving, logic optimization is increasingly pursuing exact solutions rather than suboptimal solutions. First,the logic representations and the Boolean SATisfiability(SAT) problem are briefly described. Then, the researchprogress of exact synthesis in area optimization and depth optimization of Boolean logic network at two aspects,exact synthesis algorithm and encoding, are introduced. Finally, the future trends in exact synthesis are discussed