A Wideband LO Generator for 5G FR1 Bands Using a Single LC-VCO-Based Subsampling PLL and a Ring-VCO-Based Fractional-Resolution Frequency Multiplier

被引:12
|
作者
Jo, Yongwoo [1 ]
Kim, Juyeop [1 ]
Shin, Yuhwan [1 ]
Park, Hangi [1 ]
Hwang, Chanwoong [1 ]
Lim, Younghyun [2 ]
Choi, Jaehyouk [3 ]
机构
[1] Korea Adv Inst Sci & Technol KAIST, Sch Elect Engn, Daejeon 34141, South Korea
[2] Kyung Hee Univ, Dept Elect Engn, Yongin 17104, South Korea
[3] Seoul Natl Univ, Dept Elect & Comp Engn, Seoul 08826, South Korea
基金
新加坡国家研究基金会;
关键词
5G; cascaded architecture; digital phase-locked loop (PLL); digital predistortion (DPD); frequency multiplier (FM); frequency range 1 (FR1); local oscillation (LO) generator; rms jitter; ULTRA-LOW-JITTER; RF TRANSCEIVER; CMOS;
D O I
10.1109/JSSC.2023.3321837
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this work, an ultra-low -jitter wideband cascaded local oscillation (LO) generator for 5G frequency range 1 (FR1) is presented. Using the phase-rotating divider (PRD) of the 2nd-stage ring-oscillator-based frequency multiplier (RO-FM) that can generate fractional multiplication factors (Ms), the required frequency-tuning range (FTR) of the 1st-stage phase-locked loop (PLL) dramatically decreased to 21%, which can be covered easily by a single low-phase-noise LC-voltage-controlled oscillator (VCO). Thus, the proposed LO generator can cover entire FR1 bands using only one LC tank. To suppress the fractional spurs caused by the mismatches of the delay cells of an RO, an individual-delay-cell-controllable digital loop filter (IDC-DLF) was used to calibrate the mismatches. Since the IDC-DLF equalizes the intervals between the quadrature signals of the RO, it can also naturally guarantee a precise quadrature relationship without any additional calibration. The 1st-stage PLL was designed based on a subsampling architecture, and it used a digital-to-analog converter (DAC)-based quantization error (Q-error) cancellation, dual-clock-phase generator, and a third-order curve fitting digital predistortion (TCF-DPD) to achieve ultra-low phase noise. The proposed LO generator was fabricated in a 65-nm CMOS process, and it used the power of 17.9 mW and the area of 0.64 mm(2) . The rms jitter, measured near 7.675 GHz (M=4.25), was 135 fs, and the calculatedI/Qphase error from the fractional spur level was 0.16(degrees).
引用
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页码:3338 / 3350
页数:13
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