MUX64, an analogue 64-to-1 multiplexer ASIC for the ATLAS high granularity timing detector

被引:1
|
作者
Xu, Z. [1 ]
Zhang, L.
Huang, X. [2 ]
Sha, Q. [3 ,4 ]
Ge, Z.
Che, Y. [1 ]
Gong, D. [2 ]
Hou, S. [5 ]
Zhang, J. [3 ,4 ]
Liu, T. [2 ]
Liang, Z. [3 ,4 ]
Ye, J. [2 ]
Qi, M. [1 ]
机构
[1] Nanjing Univ, Dept Phys, Nanjing 210093, Peoples R China
[2] Southern Methodist Univ, Dept Phys, Dallas, TX 75275 USA
[3] Chinese Acad Sci, Inst High Energy Phys, Beijing 100049, Peoples R China
[4] Univ Chinese Acad Sci, Beijing 100040, Peoples R China
[5] Acad Sinica, Inst Phys, Taipei 11529, Taiwan
基金
中国国家自然科学基金;
关键词
Control and monitor systems online; Detector control systems (detector and exper-iment monitoring and slow-control systems; architecture; hardware; algorithms; databases); Analogue electronic circuits;
D O I
10.1088/1748-0221/18/03/C03012
中图分类号
TH7 [仪器、仪表];
学科分类号
0804 ; 080401 ; 081102 ;
摘要
We present the design and the performance of MUX64, a 64-to-1 analogue multiplexer ASIC for the ATLAS High Granularity Timing Detector (HGTD). The MUX64 transmits one of its 64 inputs selected by six address lines for the voltages or temperatures being monitored to an lpGBT ADC channel. The prototype ASICs fabricated in TSMC 130 nm CMOS technology were prepared in wire-bonding and QFN88 packaging format. A total of 280 chips was examined for functionality and quality assurance. The accelerated aging test conducted at 85 degrees C shows negligible degradation over 16 days.
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页数:9
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