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- [1] A 3-8bit Reconfigurable Hybrid ADC Architecture with Successive-approximation and Single-slope Stages for Computing in Memory 2022 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS 22), 2022, : 3393 - 3397
- [4] A Successive Approximation ADC with Resistor-Capacitor Hybrid Structure 2013 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION, AND TEST (VLSI-DAT), 2013,
- [5] A Successive Approximation ADC with Resistor-Capacitor Hybrid Structure 2013 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION, AND TEST (VLSI-DAT), 2013,
- [8] A 10-bit 8.3MS/s switched-current successive approximation ADC for column-parallel imagers PROCEEDINGS OF 2008 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-10, 2008, : 224 - 227
- [10] A Low-Power SiPM Readout Front-end with Fast Pulse Generation and Successive-Approximation Register ADC in 0.18 μm CMOS 2019 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2019,