Verifying consistency of software product line architectures with product architectures

被引:0
|
作者
Duran-Limon, Hector A. [1 ]
Velasco-Elizondo, Perla [2 ]
Mora, Manuel [3 ]
Meda-Campana, Maria E. [1 ]
Aguilar, Karina [4 ]
Hernandez-Ochoa, Martha [5 ]
Sumuano, Leonardo Soto [1 ]
机构
[1] Univ Guadalajara, CUCEA, Guadalajara, Jalisco, Mexico
[2] Autonomous Univ Zacatecas, Zacatecas, Mexico
[3] Autonomous Univ Aguascalientes, Aguascalientes, Mexico
[4] Autonomous Univ Guadalajara, Guadalajara, Jalisco, Mexico
[5] Univ Guadalajara, CUNORTE, Guadalajara, Jalisco, Mexico
来源
SOFTWARE AND SYSTEMS MODELING | 2024年 / 23卷 / 01期
关键词
Software product lines; Software architecture; SPL Verification; Architecture verification; Ontologies; Model-driven engineering; FEATURE MODELS; MUTATION; VERIFICATION;
D O I
10.1007/s10270-023-01114-4
中图分类号
TP31 [计算机软件];
学科分类号
081202 ; 0835 ;
摘要
There has been increasing interest in modeling software product lines (SPLs) using architecture description languages (ADLs). However, sometimes it is required to reverse engineer an SPL architecture from a set of product architectures. This procedure needs to be performed manually as currently does not exist tool support to automate this task. In this case, verifying consistency between the product architectures and the reverse engineered SPL architecture is still a challenge; particularly, verifying component interconnection aspects of product architectures with respect to the commonality and variability of an SPL architecture represented in an ADL. Current approaches are unable to detect whether the component interconnections in a product architecture have inconsistencies with the component interconnections defined by the SPL architecture. To tackle these shortcomings, we developed the Ontology-based Product Architecture Verification (OntoPAV) framework. OntoPAV relies on the ontology formalism to capture the commonality and variability of SPLs architectures. Reasoning engines are employed to automatically identify component interconnection inconsistencies among SPL and product architectures. Our evaluation results show that our verifier has a high accuracy for detecting consistency errors and that it scales linearly for architectures from 1000 to 5000 architecture elements.
引用
收藏
页码:195 / 221
页数:27
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