InterPRET: a Time-predictable Multicore Processor

被引：3

作者：

Jellum, Erling Rennemo ^{[1
]}

Lin, Shaokai ^{[2
]}

Donovan, Peter ^{[2
]}

Jerad, Chadlia ^{[3
]}

Wang, Edward ^{[4
]}

Lohstroh, Marten ^{[2
]}

Lee, Edward A. ^{[2
]}

Schoeberl, Martin ^{[5
]}

机构：

[1] NTNU, Trondheim, Norway

[2] Univ Calif Berkeley, Berkeley, CA USA

[3] Univ Manouba, Manouba, Tunisia

[4] MIT, Boston, MA USA

[5] DTU, Copenhagen, Denmark

来源：

2023 CYBER-PHYSICAL SYSTEMS AND INTERNET-OF-THINGS WEEK, CPS-IOT WEEK WORKSHOPS | 2023年

基金：

美国国家科学基金会;

关键词：

ARCHITECTURE;

D O I：

10.1145/3576914.3587497

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

With the end of Moore's law and the breakdown of Dennard scaling, multicore processors are the standard way to continue improving performance while reducing Size, Weight and Power (SWaP). However, this performance is typically achieved at the cost of repeatability and predictability. Precision-timed (PRET) architectures have been shown to deliver high performance without sacrificing predictability. In this paper, we introduce InterPRET: an architecture consisting of FlexPRET cores interconnected via the S4NOC network-on-chip. Both the processor cores and the network-on-chip are time-predictable, yielding an end-to-end time-predictable architecture suitable for real-time systems.

引用

页码：331 / 336

页数：6

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