Simulated annealing-based high-level synthesis methodology for reliable and energy-aware application specific integrated circuit designs with multiple supply voltages

Integrated circuits have become more vulnerable to soft errors due to smaller transistor sizes and lower threshold voltage levels. Energy reduction methods make circuits more error-prone since even the smallest amounts of environmental radiation can cause a bit flip. Furthermore, redundancy-based error detection and correction methods induce higher costs and area overhead. Thus, several conflicting parameters may need to be considered during embedded system design (e.g., area, performance, energy, and reliability). High-level synthesis (HLS) is the most practical design step to consider all these parameters as complexity increases at lower levels. HLS can be viewed as a multi-objective optimization problem of finding a set of Pareto-optimal designs, allowing designers to choose the ones that best fit the requirements. Moreover, the number of synthesis options superlinearly affects the search space growth, necessitating efficient optimization methods. In this study, we propose simulated annealing (SA)-based HLS methods for multi-Vcc application-specific integrated circuit design, aiming to optimize energy consumption and reliability under the area and latency constraints. Furthermore, we use duplication to improve design reliability as much as the constraints allow. We compared our methods against genetic algorithm (GA)-based and integer linear programming (ILP)-based methods and showed their effectiveness in finding optimum or near-optimum results in a short running time. SA-based methods achieved up to 21.20% reliability improvement on average and up to 38% energy reduction on average, while preserving the reliability value against the GA-based metaheuristic counterpart under joint reliability and energy optimization on four HLS benchmarks.