An SEU-hardened ternary SRAM design based on efficient ternary C-elements using CNTFET technology

被引:14
|
作者
Bakhtiary, Vahid [1 ]
Amirany, Abdolah [1 ]
Moaiyeri, Mohammad Hossein [1 ]
Jafari, Kian [1 ]
机构
[1] Shahid Beheshti Univ, Fac Elect Engn, Tehran, Iran
关键词
Single-event upset (SEU); CNTFET; Radiation-hardened; Ternary C-element; SRAM; CARBON NANOTUBE TRANSISTORS; VIRTUAL-SOURCE MODEL; LOW-POWER; THRESHOLD VOLTAGE; ENERGY-EFFICIENT; LOGIC GATES; FLIP-FLOP; ROBUST; LATCH; CIRCUITS;
D O I
10.1016/j.microrel.2022.114881
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Ternary logic has been investigated for several years as it can provide substantial advantages in reducing the complexity of operations and the number of interconnects. On the other hand, with the advancement of tech-nology and the reduction of the feature size and supply voltage, the sensitivity of memory elements to radiation effects has increased. In this paper, a robust ternary SRAM (TSRAM) cell is designed using a novel ternary C -element based on carbon nanotube field-effect transistors (CNTFETs). Besides, a 2mx2n ternary memory array architecture is designed and simulated based on the proposed TSRAM cell. Unlike the previous TSRAM cells, our proposed cell is hardened against radiation effects caused by high-energy particle strikes, which is a significant achievement in ternary memory design. Our extensive simulations demonstrate that the proposed radiation -hardened TSRAM offers up to 77x higher critical charge and up to 98 % higher SNM at the cost of 47 % to 65 % area overhead. It is also noteworthy that the proposed design only needs only two threshold voltages. Moreover, the proposed TSRAM is robust against the process and temperature variations. Our results emphasize that the proposed design is a milestone for designing high-performance, radiation-hardened, and robust ternary memory chips.
引用
收藏
页数:13
相关论文
共 34 条
  • [1] SEU-hardened Dual Data Rate Flip-Flop Using C-elements
    Devarapalli, Srikanth V.
    Zarkesh-Ha, Payman
    Suddarth, Steven C.
    2010 IEEE 25TH INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS (DFT 2010), 2010, : 167 - 171
  • [2] Power efficient designs of CNTFET-based ternary SRAM
    Gadgil, Sharvani
    Sandesh, Goli Naga
    Vudadha, Chetan
    MICROELECTRONICS JOURNAL, 2023, 139
  • [3] Design of Efficient Ternary Operators for Scrambling in CNTFET Technology
    Kumre, Laxmi
    Sharma, Trapti
    ARABIAN JOURNAL FOR SCIENCE AND ENGINEERING, 2020, 45 (08) : 6729 - 6740
  • [4] Design of Efficient Ternary Operators for Scrambling in CNTFET Technology
    Laxmi Kumre
    Trapti Sharma
    Arabian Journal for Science and Engineering, 2020, 45 : 6729 - 6740
  • [5] Design of a Ternary Logic Processor Using CNTFET Technology
    Gadgil, Sharvani
    Sandesh, Goli Naga
    Vudadha, Chetan
    CIRCUITS SYSTEMS AND SIGNAL PROCESSING, 2024, 43 (09) : 5809 - 5833
  • [6] Efficient Ternary Compressor Design Using Capacitive Threshold Logic in CNTFET Technology
    Sharma, Trapti
    Kumre, Laxmi
    IETE JOURNAL OF RESEARCH, 2023, 69 (03) : 1539 - 1549
  • [7] Design, Analysis and Comparison between CNTFET Based Ternary SRAM Cell and PCRAM Cell
    Shreya, Sonal
    Sourav, Swapnil
    2015 COMMUNICATION, CONTROL AND INTELLIGENT SYSTEMS (CCIS), 2015, : 347 - 351
  • [8] Energy-Efficient Ternary Arithmetic Logic Unit Design in CNTFET Technology
    Sharma, Trapti
    Kumre, Laxmi
    CIRCUITS SYSTEMS AND SIGNAL PROCESSING, 2020, 39 (07) : 3265 - 3288
  • [9] Energy-Efficient Ternary Arithmetic Logic Unit Design in CNTFET Technology
    Trapti Sharma
    Laxmi Kumre
    Circuits, Systems, and Signal Processing, 2020, 39 : 3265 - 3288
  • [10] An energy-efficient design of ternary SRAM using GNRFETs
    Orouji, Maedeh
    Abbasian, Erfan
    Gholipour, Morteza
    INTERNATIONAL JOURNAL OF ELECTRONICS, 2024,