A Novel Scalable Array Design for III-V Compound Semiconductor-based Non-volatile Memory (UltraRAM) with Separate Read-Write Paths

The dream of achieving a universal memory that can provide robust non-volatile memory states along with low-energy operation has been the key driving force of memory research. Despite dominating the memory market, conventional charge-based memories cannot satisfy these requirements. However, UltraRAM, an oxide-free charge-based memory cell, aims to achieve both of these requirements. This device achieves non-volatility (with an endurance of over 10(7);cycles and a retention of over 1000 years) along with switching at low-voltage (+/- 2.3 V) utilizing a triple-barrier resonant tunneling (TBRT) structure made of InAs/AlSb. In this work, we propose an array design for UltraRAM-based memory devices. Our proposed memory array features separate read-write path and eliminates the possibility of accidentally switching the memory states stored in the array. Moreover, our design allows us to read all the cells in a column in one cycle without imposing any limit on the scalability. Besides, since the read operation in our proposed design is independent of the write mechanism, there is flexibility to optimize the read operation for memory and in-memory computing applications.