Design and Evaluation of Finite Field Multipliers Using Fast XNOR Cells

The current polynomial multiplication is built on conventional CMOS cells, and no major changes are explored in the standard cell library to improve the performance. Hence state-of-the-art (SOTA) finite field multipliers of operand sizes ranging from 93 to 409 bits were designed and evaluated by adopting faster XNOR cells. The hardware metrics in the form of gates usage, and propagation delay were compared. The SOTA multipliers of different approaches including Conventional Algorithm (CA), Karatsuba Algorithm (KA), Overlap free Karatsuba Algorithm (OKA), and Overlap-free based multiplication strategy (OBS) were designed and synthesized through ASIC flow using 45 nm GPDK library files. The fast XNOR cell adopted SOTA multipliers improved the compute delay in the range of 8.24% to 33.45%, 8% to 37.05%, 4.63% to 18.36%, and 1.01% to 38.73% for OKA, OBS, CA, and KA respectively. All the design files are made freely available for further usage to research and designers' community.