CMOS phase-locked loops in ISSCC 2023

As discussed previously, PLLs reported in ISSCC 2023 shows several design trends, including design digit-al-intensive calibration, cascading several stage PLLs with different architectures, performance improvement with reference frequency multiplication, and high-performance design with lower supply voltage using multi-path architectures. Hence, in summary, the PLL future performance improvements rely more and more on the architecture and circuit in-novation rather than new process. © 2023 Chinese Institute of Electronics.