Hardware design and implementation of high-speed multidimensional reconciliation sender module in continuous-variable quantum key distribution

In continuous-variable quantum key distribution systems, the multidimensional reconciliation process can correct errors in raw keys at long transmission distances, so that both communicating parties can obtain an identical set of corrected key strings. In this paper, we designed and implemented a hardware acceleration scheme for the complete multidimensional reconciliation sender module using the parallel processing capability of FPGAs. To this end, we simplified the matrix operation based on the characteristic of fewer nonzero elements at the matrix family A(8) and customized an exclusive circuit structure. In addition, we also constructed a multi-edge type (MET) LDPC code with good decoding performance and implemented a high-speed MET-LDPC decoding module based on FPGA. When the signal-to-noise ratio is 0.16, the simulation results show that the reconciliation efficiency is 93.4%, the frame error rate is 19%, and the throughput can reach 9.6 Mbps, which is two orders of magnitude higher compared with CPU. Our work paves the way for the miniaturization and integration of CV-QKD systems.