ASMPEC: Approximate-Sum-Based Mapping of Partial Products With Error Correction for Softcore Multipliers on FPGAs

被引：2

作者：

Aizaz, Zainab ^{[1
]}

Khare, Kavita ^{[1
]}

机构：

[1] Maulana Azad Natl Inst Technol, Dept Elect & Commun Engn, Bhopal 462003, India

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | 2023年 / 70卷 / 12期

关键词：

Multipliers; approximate computing; softcore multipliers; FPGA; arithmetic logic modules (ALM); BOOTH MULTIPLIERS; AREA;

D O I：

10.1109/TCSII.2023.3292947

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this brief, Approximate Softcore Multipliers are designed on Intel FPGAs to boost the energy efficiency of Error resilient Applications. Two partial products (PP) of a multiplier PP matrix are added approximately in a unique manner, to map on a six input ALM, in order to reduce the total resource utilization of the circuit. The carry generated in one column is also mapped with the sum of the next column for Error Correction. When compared to the state-of-art approximate multipliers, area savings of 6.25%-26.25% for 16-bit multipliers and minimum values of LUTx CPD x PDP for 8-bit multipliers, are achieved. Application based case study is performed on Convolutional neural networks (CNN), K-nearest neighbors algorithm (KNN) and Image multiplication.

引用

页码：4569 / 4573

页数：5