CIFER: A Cache-Coherent 12-nm 16-mm2 SoC With Four 64-Bit RISC-V Application Cores, 18 32-Bit RISC-V Compute Cores, and a 1541 LUT6/mm2 Synthesizable eFPGA

被引：1

作者：

Li, Ang ^{[1
]}

Chang, Ting-Jung ^{[2
,3
]}

Gao, Fei ^{[1
]}

Ta, Tuan ^{[4
]}

Tziantzioulis, Georgios ^{[1
]}

Ou, Yanghui ^{[4
]}

Wang, Moyang ^{[4
]}

Tu, Jinzheng ^{[1
]}

Xu, Kaifeng ^{[1
]}

Jackson, Paul ^{[1
]}

Ning, August ^{[1
]}

Chirkov, Grigory ^{[1
]}

Orenes-Vera, Marcelo ^{[2
]}

Agwa, Shady ^{[4
,5
]}

Yan, Xiaoyu ^{[4
]}

Tang, Eric ^{[4
]}

Balkind, Jonathan ^{[6
]}

Batten, Christopher ^{[4
]}

Wentzlaff, David ^{[1
]}

机构：

[1] Princeton Univ, Dept Elect & Comp Engn, Princeton, NJ 08544 USA

[2] Princeton Univ, Dept Comp Sci, Princeton, NJ 08544 USA

[3] Natl Cheng Kung Univ, Miin Wu Sch Comp, Tainan 701, Taiwan

[4] Cornell Univ, Dept Elect & Comp Engn, Ithaca, NY 14850 USA

[5] Univ Edinburgh, Sch Engn, Edinburgh EH8 9YL, Scotland

[6] Univ Calif Santa Barbara, Dept Comp Sci, Santa Barbara, CA 93106 USA

来源：

IEEE SOLID-STATE CIRCUITS LETTERS | 2023年 / 6卷

关键词：

Cache memory; computer architecture; parallel architectures; programmable logic arrays; reconfigurable architectures; system-on-chip (SoC);

D O I：

10.1109/LSSC.2023.3303111

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This letter presents CIFER, the world's first open-source, fully cache-coherent, heterogeneous many-core, CPU-FPGA system-on chips. The 12 nm, 16-mm(2) chip integrates four 64-bit, OS-capable, RISC-V application cores; three TinyCore clusters that each contain six 32-bit, RISC-V compute cores (18 in total); and an electronic design automation-synthesized, standard-cell-based eFPGA. CIFER enables the decomposition of real-world applications and tailored execution (parallelization or specialization) per decomposed task. Our evaluation shows that: 1) the TinyCore clusters increase the throughput and energy efficiency of data-and thread-parallel tasks by up to 7.95x and 7.75x over one 64-bit core, respectively; 2) the eFPGA increases the throughput and energy efficiency of hardware-accelerable tasks by up to 9.29x and 10.62x, respectively; and 3) using coherent caches for data transfer between the processors and the eFPGA increases the throughput and energy efficiency by up to 11.1x and 10.5x, respectively.

引用

页码：229 / 232

页数：4