A Low Noise Neural Recording Frontend IC With Power Management for Closed-Loop Brain-Machine Interface Application

Brain-machine Interface (BMI) with implantable bioelectronics systems can provide an alternative way to cure neural diseases, while a power management system plays an important role in providing a stable voltage supply for the implanted chip. a prototype system of power management integrated circuit (PMIC) with heavy load capability supplying artifacts tolerable neural recording integrated circuit (ATNR-IC) is presented in this work. A reverse nested miller compensation (RNMC) low dropout regulator (LDO) with a transient enhancer is proposed for the PMIC. The power consumption is 0.55 mW and 22.5 mW at standby (SB) and full stimulation (ST) load, respectively. For a full load transition, the overshoot and downshoot of the LDO are 110 mV and 71 mV, respectively, which help improve the load transient response during neural stimulation. With the load current peak-to-peak range is about 560 mu A supplied by a 4-channel stimulator, the whole PMIC can output a stable 3.3 V supply voltage, which indicates that this PMIC can be extended for more stimulating channels' scenarios. When the ATNR-IC is supplied for presented PMIC through a voltage divider network, it can amplify the signal consisting of 1 mV(pp) simulated neural signal and 20 mV(pp) simulated artifact by 28 dB with no saturation.