Bi-Directional Gated Ring Oscillator Time Integrator

被引:0
|
作者
Yuan, Fei [1 ]
Parekh, Parth [1 ]
Zhou, Yushi [2 ]
机构
[1] Toronto Metropolitan Univ, Dept Elect Comp & Biomed Engn, Toronto, ON M5B 2K3, Canada
[2] Lakehead Univ, Dept Elect & Comp Engn, Thunder Bay, ON P7B 5E1, Canada
关键词
Logic gates; Delays; Bidirectional control; Ring oscillators; Transistors; Threshold voltage; Delay lines; Time-based signal processing; all-digital time integrator; bi-directional gated ring oscillators; bi-directional gated delay lines; JITTER; NOISE; ADC;
D O I
10.1109/TCSI.2023.3300225
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper presents the principle, design, and analysis of a bi-directional gated ring oscillator (BDGRO) time integrator for time-based signal processing. The time integrator features full compatibility with technology, rapid integration, low power consumption, a virtually unlimited dynamic range, built-in dynamic element matching, and self-digitization. A detailed analysis of the impact of the imperfections of the time integrator including nonlinearity, skew, supply voltage noise, device noise, and metastability-induced gating errors is provided, supported with simulation results. The time integrator is designed in a TSMC 130 nm 1.2 V CMOS technology and analyzed using Virtuoso/Spectre with BSIM3 device models. Time integration is confirmed using simulation results in both time and frequency domains. The time integrator exhibits a clean spectrum without noticeable harmonics and consumes 0.25 mW with a gain of 15.48 dB at 20 MS/s.
引用
收藏
页码:3461 / 3473
页数:13
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