Optimized Mid-bond Order for 3D-Stacked ICs Considering Failed Bonding

被引:0
|
作者
LIANG Huaguo [1 ]
CHANG Hao [2 ,3 ]
LI Yang [2 ]
WANG Wei [2 ]
CHEN Tian [1 ]
XU Hui [2 ]
机构
[1] School of Electronic Science & Applied Physics, Hefei University of Technology
[2] School of Computer and Information, Hefei University of Technology
[3] Department of Computer Science & Technology, Anhui University of Finance & Economics
基金
国家教育部博士点专项基金资助;
关键词
3D-Stacked ICs; Through silicon via(TSV); 3D-SICs test; Sequential stacking; Rearranged stacking; Abort on fail;
D O I
暂无
中图分类号
TN407 [测试和检验];
学科分类号
080903 ; 1401 ;
摘要
One notable difference between 3D test flow and 2D test flow mainly lies in the mid-bond test, in which the stacking yield can be further enhanced through optimized bonding arrangement. In contrast to the existing sequential stacking, this paper proposes a novel rearranged stacking scheme which estimates the probability and cost of failed bonding in each stacking step and optimizes the mid-bond order to screen out the failed component as early as possible. The effect of the rearranged stacking has been extensively analyzed using the yield model and cost model of 3D-SICs considering different process parameters such as die yield, stacking size, failure rate and redundancy degree of TSVs. Experimental results demonstrate that the proposed rearranged stacking method is only a half of the sequential stacking in terms of Failed area ratio(FAR).
引用
收藏
页码:223 / 228
页数:6
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  • [1] Optimized Mid-bond Order for 3D-Stacked ICs Considering Failed Bonding
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    [J]. CHINESE JOURNAL OF ELECTRONICS, 2015, 24 (02) : 223 - 228
  • [2] Optimized Stacking Order for 3D-Stacked ICs Considering the Probability and Cost of Failed Bonding
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    [J]. 2014 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT), 2014,
  • [3] Optimization scheme for mid-bond test time on 3D-stacked ICs
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    Liang, Hua-Guo
    Jiang, Cui-Yun
    Ouyang, Yi-Ming
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    [J]. Tien Tzu Hsueh Pao/Acta Electronica Sinica, 2015, 43 (02): : 393 - 398
  • [4] Impact of Mid-Bond Testing in 3D Stacked ICs
    Taouil, Mottaqiallah
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    [J]. PROCEEDINGS OF THE 2013 IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI AND NANOTECHNOLOGY SYSTEMS (DFTS), 2013, : 178 - 183
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    Zhu X.
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    [J]. 1600, Chinese Institute of Electronics (45): : 2263 - 2271
  • [6] On Effective TSV Repair for 3D-Stacked ICs
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    Eklow, Bill
    [J]. DESIGN, AUTOMATION & TEST IN EUROPE (DATE 2012), 2012, : 793 - 798
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