Image boundary extraction based on island model genetic algorithms for integrated circuit defect detection

被引:0
|
作者
PAN Zhong-liang
机构
关键词
integrated circuit; wafer; defect detection; image processing; genetic algorithms;
D O I
暂无
中图分类号
TN407 [测试和检验];
学科分类号
080903 ; 1401 ;
摘要
The integrated circuit chip with high performance has a high sensitivity to the defects in manufacturing environments.When there are defects on a wafer,the defects may lead to the degradation of chip performance.It is necessary to design effective detection approaches for the defects in order to ensure the reliability of wafer.In this paper,a new method based on image boundary extraction is presented for the detection of defects on a wafer.The method uses island model genetic algorithms to perform the segmentation of wafer images,and gets the optimal threshold values.The island model genetic algorithm uses two distinct subpopulations,it is a coarse grain parallel model.The individuals migration can occur between the two subpopulations to share genetic materials.A lot of experimental results show that the defect detection method proposed in this paper can obtain the features of defects effectively.
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页码:207 / 211
页数:5
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  • [1] GLEASON S,FERRELL R K,KARNOWSKI TP.De- tection of semiconductor defects using a novel fractal en- coding algorithm. SPIE proceedings series: De- sign,process integration,and characterization for micro- electronics . 2002
  • [2] SHANKAR N G,ZHONG Z W.A rule-based computing approach for the segmentation of semiconductor defects. Microelectronics Journal . 2006
  • [3] BOURGEAT P,MERIAUDEAU F,GORRIA P.Gabor filters and SVM classifier for pattern wafers segmentation. SPIE proceedings series : Wavelet applications in industrial processing II . 2004
  • [4] WANG C H.Recognition of semiconductor defect patterns u-sing spatial filtering and spectral clustering. Expert Sys-tems with Applications . 2008
  • [5] HE Q,WANG J.Fault detection using the k-nearest neighbor rule for semiconductor manufacturing processes[J]. IEEE Trans.on Semiconductor Manufacturing . 2007
  • [6] MURATA T,SATO M.Reduction of wafer edge induced defect by WEE optimisation. http://ieeexplore.ieee.org/xpls/abs _ all.jsp? arnumber=4446900 . 2008
  • [7] PROTASIO D C,MARCOS D F,CARLOS S R.Circuit testing using the principles of self-nonself discrimination. IEEE Trans.on Instrumentation and Measurement . 2008
  • [8] MININNO E,CUPERTINO F,NASO D.Real-valued compact genetic algorithms for embedded microcontroller optimisation. IEEE Trans.on Evolutionary Compu- tation . 2008
  • [9] Shankar, N.G,Zhong, Z.W.Defect detection on semiconductor wafer surfaces. Microelectronics Journal . 2005
  • [10] TONG L I,WANG C H,HUANG C L.Monitoring de- fects in IC fabrication using a hotelling T-sup2 control chart. IEEE Trans.on Semiconductor Manufactur- ing . 2005