Comparative Analysis of Noise Margin Between Pure SET-SET and Hybrid SET-PMOS Inverters

Single-electron transistor (SET) is considered as one of the promising candidates for future electronic devices due to its advantages of low power consumption and high integration. The comparative analysis of SET-based inverters, especially the noise margin, is carried out. Pure SET-SET and hybrid SET with p type metal oxide semiconductor (SET-PMOS) inverters are designed for investigation. The effects of SET supply voltage, junction resistance and junction capacitance on noise tolerance and power consumption of inverters are studied. For hybrid SET-PMOS inverters, the noise margin for a logic high (NMH) is less than 60 mV under various conditions, which may become the bottleneck of its application. For pure SET-SET inverters, both NMH and the noise margin for a logic low (NML) could reach 300 mV at a supply voltage of 0.8 V. The minimum power consumption of pure SET-SET and hybrid SET-PMOS inverters is 2.85 nW and 58 nW, respectively. The pure SET-SET inverters have greater noise tolerance and lower power consumption, which is more conducive to large-scale integration. When junction capacitance C-J=0.0273 aF and junction resistance R-T >= 1 M Omega in SET-SET inverters at a supply voltage of 0.8 V, the NMH and NML are not significantly affected by the junction resistance and the noise margin fluctuates at 300 mV.