Modeling Row Hammer Effect in 3D Capacitor-less DRAM using Triple-Gated Silicon Nanosheet Device

A monolithically stackable 3D capacitor-less DRAM structure using triple-gated silicon nanosheet device is demonstrated using TCAD simulation. Our proposed device exhibits a low programming voltage of 1.8 V, a high current sense margin of 78 mu A, a fast speed of 5 ns and a data retention time of more than 104 s. In addition, we evaluate the row hammer effect on the 3D array level, including program, erase, read, and hold operations. The simulation results show a robust storage node potential despite repeated attack operations from the neighboring cell.