A 0.73 dB Multi-Gain Low Noise Amplifier Design with Fast Mode-Switching for 5G/4G Applications

被引:0
|
作者
Choi, Kyung-Duk [1 ,2 ]
Paik, Sunghwan [2 ]
Lee, Kyung-Jin [2 ]
Kim, Dong-Min [1 ,2 ]
Park, Jun-Eun [1 ]
Yoo, Sang-Sun [2 ]
Hwang, Keum-Cheol [1 ]
Yang, Youngoo [1 ]
Lee, Kang-Yoon [1 ,2 ]
机构
[1] Sungkyunkwan Univ, Dept Elect & Comp Engn, Coll Comp & Informat, Suwon 16419, South Korea
[2] SKAIChips, Suwon 16571, South Korea
关键词
RF LNA; gain mode switching; three-core input structure; cascaded switching; reconfigurable input structure;
D O I
10.3390/s24248082
中图分类号
O65 [分析化学];
学科分类号
070302 ; 081704 ;
摘要
In this paper, a sub-1dB Low Noise Amplifier (LNA) with several gain modes, including amplification and attenuation modes required for the fifth and fourth generations (5G/4G) of mobile network applications, is proposed. Its current consumption is adaptive for every gain mode and varies to lower currents for lower amplifications due to the importance of current consumption for mobile network applications. The proposed LNA features an innovative architecture with a three-core input structure supporting multi-gain modes, achieving high gain and ultra-low noise performance. Additionally, the design integrates a cascade switching mechanism to ensure fast transitions between the gain modes and maintain operational stability. A reconfigurable input structure is introduced to support multiple input stages, enabling the proposed LNA to be compatible with both 5G and 4G applications. The proposed design demonstrates the implementation of seven distinct gain modes with a maximum current consumption of 11.68 mA, achieving proper input matching in each gain mode. The LNA delivers a maximum gain of 20.4 dB with a noise figure of 0.73 dB. Moreover, the most stringent mode switching condition achieved, the ON time, is as short as 1.295 mu s, and the gain mode transition speed is an impressive 0.874 mu s, ensuring extremely fast mode transitions. The proposed LNA occupies an area of 700 mu m x 500 mu m and is fabricated using a 65 nm FD-SOI process.
引用
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页数:13
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