Enhancing Thermal Security of 3D-SiP Systems through Thermal Digital Twin (TDT)

被引:1
|
作者
Benelhaouare, Amrou Zyad [1 ]
Oukaira, Aziz [1 ]
Oumlaz, Maroua [1 ]
Lakhssassi, Ahmed [1 ]
机构
[1] Univ Quebec Outaouais UQO, Dept Engn & Comp Sci, Gatineau, PQ, Canada
关键词
Thermal attacks; Tridimentional system-in-package (3D-SiP); Thermal management; Thermal Digital Twin (TDT); COMSOL Multiphysics software; FPGA board; gradient direction sensors (GDS); thermal security; CHALLENGES; SENSOR;
D O I
10.1109/CCECE59415.2024.10667282
中图分类号
TP39 [计算机的应用];
学科分类号
081203 ; 0835 ;
摘要
Thermal attacks targeting large-scale integrated microsystems, such as three-dimensional package systems (3D-SiP), exploit thermal fluctuations to compromise their security. These attacks can lead to excessive thermal dissipation, causing hardware failures or enabling the extraction of sensitive information such as cryptographic keys by analyzing heating and cooling patterns. Therefore, the design of integrated microsystems must integrate thermal management and security to prevent vulnerabilities to such attacks. In this article, we propose an innovative approach to improve the prediction of system-inpackage (SiP) thermal dynamics by developing a thermal digital twin (TDT) using COMSOL Multiphysics software. This method accurately replicates the thermal behaviors of an existing physical system, specifically the Xilinx SPARTAN-3E field-programmable gate array (FPGA) board, using thermal data collected by the Gradient Direction Sensor (GDS) technology integrated into the Xilinx FPGA. Our TDT offers a cutting-edge solution for monitoring and examining thermal fluxes in 3D-SiPs, representing a significant advancement in the thermal regulation of these microsystems and implicitly enhancing their thermal security.
引用
收藏
页码:20 / 24
页数:5
相关论文
共 50 条
  • [1] Mitigating Thermal Side-Channel Vulnerabilities in FPGA-Based SiP Systems Through Advanced Thermal Management and Security Integration Using Thermal Digital Twin (TDT) Technology
    Benelhaouare, Amrou Zyad
    Mellal, Idir
    Oumlaz, Maroua
    Lakhssassi, Ahmed
    ELECTRONICS, 2024, 13 (21)
  • [2] Actual stresses around TSV in whole 3D-SiP under reflow or power ON/OFF thermal load
    Kinoshita, Takahiro
    Kawakami, Takashi
    Wakamatsu, Takeshi
    Shima, Shunpei
    Matsumoto, Keiji
    Kohara, Sayuri
    Yamada, Fumiaki
    Orii, Yasumitsu
    2012 7TH INTERNATIONAL MICROSYSTEMS, PACKAGING, ASSEMBLY AND CIRCUITS TECHNOLOGY CONFERENCE (IMPACT), 2012,
  • [3] Review on the through Silicon Via Technology in the 3D-system in Package (3D-SiP)
    Wang, Meiyu
    Zhang, Haobo
    Hu, Weibo
    Mei, Yunhui
    Jixie Gongcheng Xuebao/Journal of Mechanical Engineering, 2024, 60 (19): : 261 - 276
  • [4] Silicon through-hole interconnection for 3D-SiP using room temperature bonding
    Tanaka, Naotaka
    Yoshimura, Yasuhiro
    Naito, Takahiro
    Akazawa, Takashi
    ENABLING TECHNOLOGIES FOR 3-D INTEGRATION, 2007, 970 : 125 - +
  • [5] THERMAL STRESS OF THROUGH SILICON VIAS AND SI CHIPS IN 3D SIP
    Kinoshita, Takahiro
    Kawakami, Takashi
    Hori, Tatsuhiro
    Matsumoto, Keiji
    Kohara, Sayuri
    Orii, Yasumitsu
    Yamada, Fumiaki
    Kada, Morihiro
    PROCEEDINGS OF THE ASME PACIFIC RIM TECHNICAL CONFERENCE AND EXHIBITION ON PACKAGING AND INTEGRATION OF ELECTRONIC AND PHOTONIC SYSTEMS, MEMS AND NEMS 2011, VOL 1, 2012, : 325 - +
  • [6] Thermal Stresses around Void in Through Silicon Via in 3D SiP
    Kinoshita, Takahiro
    Sugiura, Tomoya
    Kawakami, Takashi
    Matsumoto, Keiji
    Kohara, Sayuri
    Orii, Yasumitsu
    2014 INTERNATIONAL CONFERENCE ON ELECTRONICS PACKAGING (ICEP), 2014, : 105 - 108
  • [7] 3D eWLB (embedded wafer level BGA) Technology for 3D-Packaging/3D-SiP (Systems-in-Package) Applications
    Yoon, Seung Wook
    Bahr, A.
    Baraton, X.
    Marimuthu, Pandi Chelvam
    Carson, Flynn
    2009 11TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE (EPTC 2009), 2009, : 915 - +
  • [8] Numerical Modeling of the Thermal Performance of 3D SiP with TSV
    Pan, Kailin
    Huang, Jing
    Liu, Jing
    Zhu, Weitao
    Ren, Guotao
    MANUFACTURING PROCESS TECHNOLOGY, PTS 1-5, 2011, 189-193 : 1610 - 1613
  • [9] Low-cost through-hole electrode interconnection for 3D-SiP using room-temperature bonding
    Tanaka, Naotaka
    Yoshimura, Yasuhiro
    Naito, Takahiro
    Miyazaki, Chuichi
    Uematsu, Toshihide
    Hanada, Kenji
    Toma, Norihisa
    Akazawa, Takashi
    56TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE 2006, VOL 1 AND 2, PROCEEDINGS, 2006, : 814 - +
  • [10] THERMAL STRESS SIMULATION FOR 3D SIP WITH TSV STRUCTURE UNDER UNSTEADY THERMAL LOADS
    Kinoshita, Takahiro
    Kawakami, Takashi
    Sugiura, Tomoya
    Matsumoto, Keiji
    Kohara, Sayuri
    Orii, Yasumitsu
    INTERNATIONAL TECHNICAL CONFERENCE AND EXHIBITION ON PACKAGING AND INTEGRATION OF ELECTRONIC AND PHOTONIC MICROSYSTEMS, 2015, VOL 2, 2015,