Studies and Application of Failure Analysis Technology for Semiconductor Advanced Processes

In failure analysis, the test is widely used for chip delayer and the probe to the anatomy and electrical testing, traditional to delayer can only from the surface of the chip to the whole strip of metal layer, limitation and manual work, of course, generally cannot assure flatness, so pay attention to the position of general only one, for the failure of multiple locations chips, not thorough observation, The traditional probe test can only test the electrical properties from the front of the chip, but not the internal structure of the chip. If the chip has multiple failure locations, or the failure location is on the metal layer inside the chip, the conventional delayer may not be able to see the full picture of the failure, especially for high-order chips, the traditional delayer method has been unable to meet the smoothness and accuracy of the analysis; Due to the size of the tip, the conventional probe cannot conduct electrical testing and failure location on the metal layer after the chip is removed. As a result, the analysis may fail. In this study, we propose a new test method that improves the speed and accuracy of failure analysis by using the state-of-the-art Plasma-FIB and Nano-Probe FA tools, which enable precise delayer and horizontal stripping of the film, thereby determining the layer structure and defect origin of the film layer identified. In particular, when used in conjunction with nanoprobe technology, state-of-the-art analytical techniques can be achieved to obtain semiconductor-transistor level parameters and defects.