Power Reduction of Montgomery Multiplication Architectures Using Clock Gating

This work presents an analysis of the power consumption of different radix implementations of Montgomery multiplication (MM). Different MM architectures are discussed and a new modified architecture for the radix-2 processing element (PE), where conversion from carry save representation to conventional representation is accomplished without using a Carry Propagate Adder (CPA) is presented in this paper. The proposed radix-2 architecture also eliminates race conditions by avoiding incorrect data selection of the multiplier bit by a processing element, by using a register. Also, the overall architectural power consumption is reduced by applying the clock gating technique to the proposed radix-2 architecture and also the high radix architecture used in this paper. Power, Performance, and Area (PPA) analysis is performed using TSMC 28hpc+ 28 nm to understand the trade-off requirements between the implementations. The results indicate that radix-2 architecture occupies lower area compared to high radix i.e. radix-16 and radix-216 implementations but the high radix architectures take less number of clock cycles than the radix-2 architecture.