Thermal metrology for deeply buried low-thermal-resistance interfaces

High heat fluxes generated in electronic devices must be dissipated by conduction through the semiconductor substrate and packaging layers to avoid local high-temperature hotspots that govern device reliability. Deeply buried interfaces within the semiconductor components are challenging to characterize in situ due to their low relative magnitude and location within the chip stack. Here, we develop a novel metrology technique and experimentally demonstrates a non-destructive method for characterization of the thermal interfacial resistances of interfaces buried within stacks of material substrates. This work targets interfaces buried deeper than the thermal penetration depth of available transient measurement techniques, but with thermal resistances below the resolution of most steady-state techniques, on the order of 0.01 cm2 K -1 W-1. This new interfacial conductance measurement technique combines non-contact periodic heating with infrared (IR) thermal sensing to measure the transient temperature response of a multi-layer stack of materials. Specifically, periodic heating of one face and cooling on the opposite phase generates a transient, one-dimensional temperature gradient across the sample stack. The corresponding steady periodic temperature amplitude and phase delay across the thickness of the material are used to extract for the thermal interfacial resistance using an inverse fitting method, assuming the thermal properties of the solid layers are known. Numerical simulations are developed to generate synthetic temperature data, which along with the inverse fitting method, are used to validate the extraction of interfacial thermal resistance in two-layer stacked materials, as well as thermal conductivity of bulk materials without an interface. The data extraction process is shown to accurately extract the interfacial thermal resistances ranging from 0.001 to 1 cm2 K -1 W -1 for interfaces that up to 5 millimeters from the exposed surface. For bulk materials, this technique demonstrates accuracy in extracting the thermal conductivity spanning a thermal conductivity range of 0.1 to 2000 W m -1 K-1. An experimental facility is developed, which includes an IR-transparent heat sink, laser-based heating, and two IR temperature sensors for measurements of thermally opaque samples. Measurements demonstrate the accuracy and sensitivity of the measurement technique for interfacial thermal resistance of two-layer samples, as well as thermal conductivity of bulk materials. The ultimate goal of this work is to develop a standardized technique for measurement of thermal resistances across the range of magnitudes and stack geometries commonly found in modern electronic packages, ranging from near-junction epitaxial semiconductor films to interconnect layers in emerging die-to-die and wafer hybrid bonding technologies.