Efficient fault tolerance and diagnosis mechanism for Network-on-Chips

The Network-on-Chip (NoC) integrates all components within a System-on-Chip (SoC), positioning itself as the SoC's most critical element. The interconnection network, which forms the foundational topology of the NoC, significantly impacts its performance. As network scale and complexity increase, the inevitability of faults emerges, underscoring the crucial need for robust fault tolerance. In this paper, we introduce a novel conditional fault model, the partial block fault (PBF) model, aimed at enhancing network fault tolerance. This model addresses the distribution of faulty node and guarantees that, even after their removal, the remaining networks maintain normal communication. Leveraging this model, we examine the fault-tolerant capability of k-ary m-cube networks Qkm and provide a theoretical analysis demonstrating the network's connectivity. We then present an O(N log N) algorithm, named DIAG-PBF, designed to ascertain the status of nodes in Qk m while allowing for the sacrifice of some fault-free nodes, where N represents the total number of nodes in Qkm. Performance analysis indicates that our fault tolerance results surpass previously known benchmarks. Additionally, experimental evaluations reveal that our approach supports a low transmission failure rate, further validating its efficacy.