Methodology for optimization of electrical parameters in the design of very large-scale integrated circuits

被引:0
|
作者
Yue, Guang [1 ]
Ren, Lin [2 ]
Wu, Xianwei [3 ]
机构
[1] Department of Automation, Taiyuan Institute of Technology, Shanxi, Taiyuan,030008, China
[2] Department of Electronic Engineering, Taiyuan Institute of Technology, Shanxi, Taiyuan,030008, China
[3] State Key Laboratory of Mechanics and Control for Aerospace Structures, Nanjing University of Aeronautics and Astronautics, Jiangsu, Nanjing,210016, China
关键词
Constrained optimization - Electric network parameters - Integrated circuit design - Reinforcement learning;
D O I
10.2478/amns-2024-2651
中图分类号
学科分类号
摘要
In this paper, we first establish a model of ultra-large-scale integrated circuits and study the model architecture from basic circuit units to complex circuit units. Then, the circuit optimization problem is mathematically analyzed, and the unconstrained and constrained parametric optimization problems with electrical parameters are investigated. Reinforcement learning is introduced to a reasonably one-to-one correspondence between the parametric optimization problem and the environment in reinforcement learning, which transforms the ordinary optimization problem into a task of reinforcement learning and realizes the optimization of electrical parameters in integrated circuit design. Finally, the effect of optimizing the electrical parameters of the method in this paper is evaluated. In the case of 200 DPPM, 300 DPPM, and 400 DPPM, the number of censored test parameters of this paper's method is distributed in the range of (10,15), while the number of censored test parameters of the other methods are in the interval of (2,10), and this paper's method outperforms the other methods. This study has an important reference value to improve the efficiency, reliability, and performance of integrated circuit design, and can provide a reference for the design of integrated circuits. © 2024 Guang Yue et al., published by Sciendo.
引用
收藏
相关论文
共 50 条
  • [1] Integrating Operations Research into Very Large-Scale Integrated Circuits Placement Design: A Review
    Zhang, Binqi
    Zhen, Lu
    Wang, Shuaian
    Yang, Fajun
    ASIA-PACIFIC JOURNAL OF OPERATIONAL RESEARCH, 2024, 41 (06)
  • [2] INTEGRATED SEMICONDUCTOR CIRCUITS APPROACH VERY LARGE-SCALE INTEGRATION
    RUCHARDT, H
    NACHRICHTENTECHNISCHE ZEITSCHRIFT, 1978, 31 (09): : 660 - 668
  • [3] VERY LARGE-SCALE INTEGRATED CMOS BUFFER DESIGN
    RAYAPATI, VN
    MAHAPATRA, S
    MICROELECTRONICS AND RELIABILITY, 1989, 29 (06): : 1021 - 1033
  • [4] Advanced Fabrication Processes for Superconducting Very Large-Scale Integrated Circuits
    Tolpygo, Sergey K.
    Bolkhovsky, Vladimir
    Weir, T. J.
    Wynn, Alex
    Oates, D. E.
    Johnson, L. M.
    Gouker, M. A.
    IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 2016, 26 (03)
  • [5] VERY LARGE-SCALE INTEGRATED-CIRCUITS (VLSI) AND FUTURE OF COMPUTER
    KOBAYASHI, T
    FUJITSU SCIENTIFIC & TECHNICAL JOURNAL, 1977, 13 (04): : 1 - 19
  • [6] Design-in for EMC on CMOS large-scale integrated circuits
    Steinecke, T
    2001 IEEE EMC INTERNATIONAL SYMPOSIUM, VOLS 1 AND 2, 2001, : 910 - 915
  • [7] ON THE COMPLEXITY OF VERY LARGE-SCALE INTEGRATED-CIRCUIT DESIGN
    CARTER, HW
    LARGE SCALE SYSTEMS IN INFORMATION AND DECISION TECHNOLOGIES, 1985, 8 (01): : 59 - 69
  • [8] Large-scale photonic integrated circuits
    Nagarajan, R
    Joyner, CH
    Schneider, RP
    Bostak, JS
    Butrie, T
    Dentai, AG
    Dominic, VG
    Evans, PW
    Kato, M
    Kauffman, M
    Lambert, DJH
    Mathis, SK
    Mathur, A
    Miles, RH
    Mitchell, ML
    Missey, MJ
    Murthy, S
    Nilsson, AC
    Peters, FH
    Pennypacker, SC
    Pleumeekers, JL
    Salvatore, RA
    Schlenker, RK
    Taylor, RB
    Tsai, HS
    Van Leeuwen, MF
    Webjorn, J
    Ziari, M
    Perkins, D
    Singh, J
    Grubb, SG
    Reffle, MS
    Mehuys, DG
    Kish, FA
    Welch, DF
    IEEE JOURNAL OF SELECTED TOPICS IN QUANTUM ELECTRONICS, 2005, 11 (01) : 50 - 65
  • [9] INTEGRATED DESIGN TOOLS FOR VERY LARGE-SCALE CELLULAR ARCHITECTURES
    SIGNORINI, J
    MICROPROCESSING AND MICROPROGRAMMING, 1991, 31 (1-5): : 37 - 42
  • [10] Metallography of very large scale integrated circuits
    Metallographie an hochintegrierten Schaltkreisen
    Burger, K., 1990, (27):