Power Optimization of Multi-Level MPRM Logic Circuits

被引：0
|
作者：
Zhao Z. [1 ]
Chu Z. [1 ]
Wang L. [1 ]
Xia Y. [1 ]
机构：
[1] Faculty of Electrical Engineering and Computer Science, Ningbo University, Ningbo
来源：
Jisuanji Fuzhu Sheji Yu Tuxingxue Xuebao/Journal of Computer-Aided Design and Computer Graphics | 2024年 / 36卷 / 04期
关键词：
logic synthesis; multi-level mixed-polarity Reed-Muller; power optimization;
D O I：
10.3724/SP.J.1089.2024.19951
中图分类号：
学科分类号：
摘要：
In this paper, multi-level mixed-polarity Reed-Muller (MPRM) power optimization is addressed by tabular technique and onset table methods. The low-power model of multi-input AND/XOR gates and tabular technique enable us to traverse the optimal power circuit of the two-level MPRM under all polarities for each cut set of the circuit. The onset table is then used to optimize multi-level MPRM based on two-level MPRM circuits. Based on our experimental results on the MCNC and EPFL benchmark suites, our algorithm improved power by 49.90% and 27.87% respectively, compared to the original circuit. Compared to the two-levels MPRM power optimization algorithm, the average area optimization rate of our algorithm is 20.52%, and the average power optimization rate is 21.24%. © 2024 Institute of Computing Technology. All rights reserved.
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页码：615 / 624
页数：9
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