Optoelectronic backplane for parallel computing

被引：0
|
作者：
Wijetunga, P. [1 ]
Sondeen, J. [1 ]
Levi, A.F.J. [1 ]
机构：
[1] Univ of Southern California, Los Angeles, CA, United States
来源：
Pacific Rim Conference on Lasers and Electro-Optics, CLEO - Technical Digest | 2000年
关键词：
Bandwidth - CMOS integrated circuits - Computational complexity - Integrated optoelectronics - Network protocols - Optical interconnects - Optics;
D O I：
10.1109/cleo.2000.907354
中图分类号：
学科分类号：
摘要：
A 32 Gbit/s, 4-port switch integrated circuit was designed and tested in CMOS technology. At a rate of 2.0 Gbit/s the integrated circuit had a worst case output phase margin. A scaled version of the integrated circuit, integrating both the CMOS and the optics, could support 64 processors at an interconnect bandwidth. The switch integrated circuit was further scaled to support networks with greater than 64 processors and its use in hierarchically-connected fixed receiver path networks.
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页码：534 / 535
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