共 50 条
- [3] Two systolic architectures for multiplication in GF(2m) IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES, 2000, 147 (06): : 375 - 382
- [7] Multiplication in GF(2m): area and time dependency/efficiency/complexity analysis 10TH IFAC WORKSHOP ON PROGRAMMABLE DEVICES AND EMBEDDED SYSTEMS (PDES 2010), 2010, : 28 - 33
- [9] A Unified VLSI Architecture for Addition and Multiplication in GF(2m) 2015 INTERNATIONAL SYMPOSIUM ON SIGNALS, CIRCUITS AND SYSTEMS (ISSCS), 2015,
- [10] Hardware Implementation and Performance Comparison of Normal Basis Multiplication Methods Over GF (2m) 2017 2ND IEEE INTERNATIONAL CONFERENCE ON WIRELESS COMMUNICATIONS, SIGNAL PROCESSING AND NETWORKING (WISPNET), 2017, : 2241 - 2247