ALGORITHM TO TRACE A PATH FOR WIRING BETWEEN CIRCUITS.

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作者：

Habra, R.R.

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| 1600年 / 17期

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Compendex;

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ELECTRIC NETWORKS

引用

共 50 条

[1] WIRING FOR HIGH-SPEED CIRCUITS.
DeClue, Joseph L.
Electronic Design, 1976, 24 (11) : 84 - 86
[2] PREDICTING THE PROBABILITY OF SHORT CIRCUITS IN METALLIZATION OR WIRING IN INTEGRATED CIRCUITS.
Forslund, D.C.
Greenberg, E.P.
IBM Technical Disclosure Bulletin, 1972, 15 (06): : 1743 - 1745
[3] Wiring Algorithms for Very Large Scale Integrated Circuits.
Rothermel, Hans-Juergen
Fortschritt-Berichte der VDI-Zeitschriften, Reihe 10: Angewandte Informatik, 1984, (32):
[4] COMPILING PATH EXPRESSIONS INTO VLSI CIRCUITS.
Anantharaman, T.S.
Clarke, E.M.
Foster, M.J.
Mishra, B.
1987, : 305 - 355
[5] OPTIMUM WIRING CONNECTIONS FOR SINGLE-METAL LEVEL INTEGRATED CIRCUITS.
Caldwell, L.B.
Crocetti, M.F.
Day, K.F.
Dunham, B.
IBM technical disclosure bulletin, 1983, 26 (06): : 2842 - 2845
[6] EFFICIENT ALGORITHM FOR ANALYSIS OF SCR CIRCUITS.
Dutta, Anup T.
Narayanan, H.
Revankar, G.N.
IETE Journal of Research, 1982, 28 (09) : 487 - 491
[7] Buyer Integrates. Cooperation in Shaping of Wiring Layout in the Manufacture of Integrated Circuits.
Renschke, Joachim
Elektronikpraxis, 1981, 16 (10): : 50 - 52
[8] HIGH RELIABILITY DYNAMIC SWITCHING OF DATA TRANSFER PATH AND CIRCUITS.
Blum, A.R.
Irro, F.
Sonntag, G.U.
IBM Technical Disclosure Bulletin, 1973, 16 (06): : 1855 - 1856
[9] PATH SET SENSITISATION PROCEDURE FOR GENERATING TESTS FOR COMBINATIONAL CIRCUITS.
Sapiecha, K.
Digital Processes, 1976, 2 (04): : 307 - 320
[10] Telephone circuits.
Perry, J
PROCEEDINGS OF THE PHYSICAL SOCIETY OF LONDON, 1910, 22 : 0252 - 0272

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