Precise control and resizing of polysilicon gate length by hard-mask etching

In this paper, we describe the etching of hard SiON/SiN masks for the reactive ion etching (RIE) of gate polycrystalline silicon (polysilicon) to precisely control and reduce gate length in order to transcend the resolution limit of lithography. A mixture of C3F8 and oxygen is used to control gate length. To improve gate critical dimension (CD) accuracy in the wafer, radical etch rate during hard-mask etching is controlled by changing the electrode gap and the temperature distribution in the wafer. The amount of CD shift is successfully controlled by optimizing the oxygen flow rate without increasing its deviation. Consequently, a 0.24-μm-wide resist pattern can be successfully resized to a polysilicon gate electrode of 0.2 μm length, Moreover, etching of both hard-mask and polysilicon does not increase the CD deviation of the polysilicon gate electrode length at the least.