BiCMOS front-end system with binary delay line for capacitive detector read-out

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Univ of Tokyo, Tokyo, Japan [1 ]
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IEEE J Solid State Circuits | / 1卷 / 98-108期
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The author would like to thank IMEC/Leuven; Belgium; for the CAD support and the electronics department ETRO/VUB at his University for the use of the infrastructure. He is also grateful to Prof. B. Wooley; CIS; Stanford University; for putting at his disposal the very instructive Ph.D. dissertations of J.-T. Wu and B. Razavi. Gratitude also goes to K. Bernier from UCL; Louvain-la-Neuve; who coordinated the irradiations;
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