SIMPLE BUT EFFECTIVE METHOD OF ELECTRICAL CONNECTIONS CHECKING OF IC LAYOUT AND ITS IMPLEMENTATION.

被引：0
|
作者：
Galenski, Janusz [1 ]
机构：
[1] Inst of Electron Technology, Warsaw, Pol, Inst of Electron Technology, Warsaw, Pol
来源：
Electron Technology (Warsaw) | 1985年 / 17卷 / 1-2期
关键词：
INTEGRATED CIRCUIT MANUFACTURE;
D O I：
暂无
中图分类号：
学科分类号：
摘要：
An approach to the problem of verification of electrical connections in IC layout in a hierarchical IC design system is presented. This approach is based on distinguishing the electrical tracks in layout description. Advantages of this solution resulting from the nonstandard electrical checking scheme are given. Finally, multivariant electrical checks of contact windows are described, and an example set of tests is given. The solution is independent of the technology of IC fabrication.
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页码：71 / 76
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