ANALYSIS OF SIGNATURE TESTABILITY OF DIGITAL NETWORK ELEMENTS.

被引：0

作者：

Yarmolik, V.N.

机构：

来源：

Automatic Control and Computer Sciences | 1987年 / 21卷 / 06期

关键词：

COMPUTER METATHEORY - Boolean Functions - LOGIC CIRCUITS; COMBINATORIAL; -; Testing;

D O I：

暂无

中图分类号：

学科分类号：

摘要：

The author demonstrates the need for analyzing signature testability of digital circuits that are investigated by compact testing methods. Conditions for signature testability of single stuck-at faults of combination circuits are given. Ways are considered of reducing the labor involved in analyzing signature testability, through reduction of the number of signatures to be examined. For the example under consideration, the number of calculated signatures is reduced by a factor of two.

引用

页码：68 / 72

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