Design of high speed bipolar Si/SiGe ICS for optical wide band communications

Si/SiGe bipolar technology has turned out to be a powerful basis for the design of high speed ICs for 40 Gbit/s ETDM communications systems. In this paper, we discuss design issues set up by system demands and existent performance limitations in terms of power consumption, speed and reliability. We present appropriate optimization measures such as active pull down techniques that serve to improve the speed and power consumption of binary digital high-speed ICs. Further advances can be achieved by applying low-level line codes. In particular, 4-level digital signal processing, where 40 Gbit/s are transmitted at 20 Gbaud/s, is very advantageous since it enables new ways for improving circuit and system performance. We will present issues, demands, design approaches and benefits of using 4-level techniques in coding and decoding-circuits for the binary-to-4-level conversion in ETDM optical communications systems. The discussion of these measures is illustrated by extensive circuit simulations based on an industrial Si/SiGe bipolar technology.