共 21 条
- [1] DETAILED ANALYSIS HELPS YOU REDUCE GATE ARRAYS POWER-CONSUMPTION EDN MAGAZINE-ELECTRICAL DESIGN NEWS, 1985, 30 (07): : 229 - 236
- [2] DETAILED GEOGRAPHIC ANALYSIS OF RESIDENTIAL ENERGY CONSUMPTION. 1703, AIChE, New York, NY (2 SAE):
- [6] Low power digital design in FPGAs: A study of pipeline architectures implemented in a FPGA using a low supply voltage to reduce power consumption. ISCAS 2000: IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - PROCEEDINGS, VOL V: EMERGING TECHNOLOGIES FOR THE 21ST CENTURY, 2000, : 561 - 564
- [7] An Analysis of the Read Margin and Power Consumption of Crossbar ReRAM Arrays TENCON 2015 - 2015 IEEE REGION 10 CONFERENCE, 2015,
- [10] ELECTRIC MOTORS AND COMPUTER-ANALYSIS REDUCE POWER-CONSUMPTION BILLS FOOD ENGINEERING, 1980, 52 (08): : 183 - 183