SILICON INTEGRATED CIRCUIT FABRICATION PROCESS MODELLING AND SIMULATION.

The paper shows a computer based method, developed at the Department of Electronic Devices, Technical University, Budapest, for modelling the steps of the up-to-date silicon integrated circuit planar technology: diffusion, ion implanation, oxidation, chemical predeposition, photolitography, etching. Simulation helps predicting electrical parameters of the semiconductor structure (sheet resistances, current gains, MOS threshold voltage, etc. ) during each of the technological steps. The simulation can involve all common donor or acceptor dopants (more impurity species as well) and the method also takes the interactions between the dopants into consideration. The results obtained by simulation can be used as input data for a physical modelling computer program, for the optimum design, and subsequently, for the automation of technology.