High-level controllability and observability analysis for test synthesis

In this study, we present a high-level testability analysis technique that evaluates the testability of a design based on the proposed controllability and observability measures. The control-data flow graph (CDFG) constructed from the VHDL description of a design is first analyzed to identify hard-to-control conditional branches and hard-to-control/observe register transfer statements. After the hard-to-test areas of the design are identified, the proposed testability enhancement methods can be applied to improve the testability of the circuit. Unlike many recent studies in the area of high-level test synthesis (HLTS) that focus on improving the testability of data paths, our approach also improves the testability of synthesized circuits by enhancing the controllability of the control flow. Experimental results on several high-level synthesis benchmarks show that when this approach is used prior to logic synthesis, the test generation complexities are reduced while better fault coverage and ATPG efficiency are often achieved. Implementation of this technique requires minimal logic and performance overheads and allows test vectors to be applied at clock-speed.