Clock and data recovery for 1.25Gb/s ethernet transceiver in 0.35μm CMOS

被引:0
|
作者
Iravani, Kamran [1 ]
Saleh, Farid [1 ]
Lee, Donald [1 ]
Fung, Patrick [1 ]
Ta, Paul [1 ]
Miller, Gary [1 ]
机构
[1] VLSI Technology, Inc, San Jose, United States
关键词
D O I
暂无
中图分类号
学科分类号
摘要
引用
收藏
页码:261 / 264
相关论文
共 50 条
  • [1] Clock and Data recovery for 1.25Gb/s ethernet transceiver in 0.35μm CMOS
    Iravani, K
    Saleh, F
    Lee, D
    Fung, P
    Ta, P
    Miller, G
    [J]. PROCEEDINGS OF THE IEEE 1999 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 1999, : 261 - 264
  • [2] A 1.25Gb/s, 460mW CMOS transceiver for serial data communication
    Chen, DL
    Baker, MO
    [J]. 1997 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE - DIGEST OF TECHNICAL PAPERS, 1997, 40 : 242 - 243
  • [3] A 1.25Gb/s half-rate clock and data recovery circuit
    Yan, CY
    Lee, CH
    Lee, Y
    [J]. 2005 IEEE VLSI-TSA INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION & TEST (VLSI-TSA-DAT), PROCEEDINGS OF TECHNICAL PAPERS, 2005, : 116 - 119
  • [4] 1.25Gb/s burst-mode optical receiver for the Ethernet PON using 0.35um CMOS technology
    Ko, HS
    Sub-Han
    Lee, MS
    Chai, SH
    [J]. 6TH INTERNATIONAL CONFERENCE ON ADVANCED COMMUNICATION TECHNOLOGY, VOLS 1 AND 2, PROCEEDINGS: BROADBAND CONVERGENCE NETWORK INFRASTRUCTURE, 2004, : 877 - 880
  • [5] 1.25Gb/s low jitter dual-loop clock and data recovery circuit
    Liu, Wei
    Xiao, Lei
    Yang, Lianxing
    [J]. ASICON 2007: 2007 7TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS, 2007, : 311 - 314
  • [6] 2.488 Gbit/s clock and data recovery circuit in 0.35 μm CMOS
    Institute of RF-and OE-ICs, Southeast University, Nanjing 210096, China
    [J]. J. Southeast Univ. Engl. Ed., 2006, 2 (143-147):
  • [7] Burst-mode transmitter for 1.25Gb/s ethernet PON applications
    Oh, YH
    Le, Q
    Lee, SG
    Yen, NDB
    Kang, HY
    Yoo, TW
    [J]. ESSCIRC 2004: PROCEEDINGS OF THE 30TH EUROPEAN SOLID-STATE CIRCUITS CONFERENCE, 2004, : 283 - 286
  • [8] A 1.25-Gb/s CMOS burst-mode optical transceiver for ethernet PON system
    Nishimura, K
    Kimura, H
    Watanabe, M
    Nagai, T
    Nojima, K
    Gomyo, K
    Takata, M
    Iwamoto, M
    Asano, H
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2005, 40 (04) : 1027 - 1034
  • [9] A monolithic 1.25Gbits/sec CMOS clock/data recovery circuit for fibre channel transceiver
    Wu, L
    Chen, H
    Nagavarapu, S
    Geiger, R
    Lee, E
    Black, W
    [J]. ISCAS '99: PROCEEDINGS OF THE 1999 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 2: ANALOG AND DIGITAL CIRCUITS, 1999, : 565 - 568
  • [10] An integrated 0.35 μm CMOS optical receiver with clock and data recovery circuit
    Chen, Yi-Ju
    du Plessis, Monuko
    [J]. MICROELECTRONICS JOURNAL, 2006, 37 (09) : 985 - 992