Interconnection delay in high-speed multi chip modules

In high-speed, high-performance design of a Multi Chip Module (MCM), it is often to reach an under-damped state in a small oscillation to result in fast and stable signal propagation. Many papers have been published on the study of interconnection delay. In most cases, however, the interconnection delay has been analyzed by using over-damped state or under-damped state in a large oscillation output. It corresponds to interconnection levels on a Printed Circuit Board (PCB) and large scale integrated circuit. And the interconnection delay for high-speed LSI has also been analyzed in the same way because of a reasonable compromise between accuracy and speed. If using this way to study interconnection delay in MCM, there would be large error or inefficiency. A formal analysis of the interconnection delay in MCM circuits is presented. Depending upon the circuit parameters, three delay formulas are respectively derived for the three delay domains.