250-MHz 5-W PowerPC microprocessor with on-chip L2 cache controller

被引：0
|
作者：
Somerset Design Cent, Austin, United States [1 ]
机构：
来源：
IEEE J Solid State Circuits | / 11卷 / 1635-1649期
关键词：
D O I：
暂无
中图分类号：
学科分类号：
摘要：
引用
收藏
相关论文
共 9 条
  • [1] A 250-MHz 5-W PowerPC microprocessor with on-chip L2 cache controller
    Gerosa, G
    Alexander, M
    Alvarez, J
    Croxton, C
    DAddeo, M
    Kennedy, AR
    Nicoletta, C
    Nissen, JP
    Philip, R
    Reed, P
    Sanchez, H
    Taylor, SA
    Burgess, B
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1997, 32 (11) : 1635 - 1649
  • [2] A 250MHz 5W RISC microprocessor with on-chip L2 cache controller
    Reed, P
    Alexander, M
    Alvarez, J
    Brauer, M
    Chao, CC
    Croxton, C
    Eisen, L
    Le, T
    Ngo, T
    Nicoletta, C
    Sanchez, H
    Taylor, S
    Vanderschaaf, N
    Gerosa, G
    1997 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE - DIGEST OF TECHNICAL PAPERS, 1997, 40 : 412 - 413
  • [3] L2 cache/controller runs 66-MHz PowerPC
    不详
    COMPUTER DESIGN, 1996, 35 (01): : 126 - 129
  • [4] DSPs deliver on-chip L2 cache and 2000 MIPS
    Levy, M
    EDN, 1998, 43 (19) : 20 - 20
  • [5] Improving the Reliability of On-chip L2 Cache Using Redundancy
    Bhattacharya, K.
    Kim, S.
    Ranganathan, N.
    2007 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN, VOLS, 1 AND 2, 2007, : 224 - 229
  • [6] A 4-MB on-chip L2 cache for a 90-nm 1.6-GHz 64-bit microprocessor
    McIntyre, H
    Wendell, D
    Lin, KJ
    Kaushik, P
    Seshadri, S
    Sundararaman, AWV
    Wang, P
    Kim, S
    Hsu, WJ
    Park, HC
    Levinsky, G
    Lu, JJ
    Heald, MCR
    Lazar, P
    Dharmasena, S
    Dharmasena, S
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2005, 40 (01) : 52 - 59
  • [7] A 4MB on-chip L2 cache for a 90nm 1.6GHz 64b SPARC microprocessor
    Wendell, D
    Lin, J
    Kaushik, P
    Seshadri, S
    Wang, A
    Sundararaman, V
    Wang, P
    McIntyre, H
    Kim, S
    Hsu, W
    Park, H
    Levinsky, G
    Lu, J
    Chirania, M
    Heald, R
    Lazar, P
    2004 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE, DIGEST OF TECHNICAL PAPERS, 2004, 47 : 66 - 67
  • [8] Utilization of the on-chip L2 cache area in CC-NUMA multiprocessors for applications with a small working set
    Chung, SW
    Kim, HS
    Jhon, CS
    IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2004, E87D (07): : 1617 - 1624
  • [9] A Power-Efficient 3-D On-Chip Interconnect for Multi-Core Accelerators with Stacked L2 Cache
    Kang, Kyungsu
    Park, Sangho
    Lee, Jong-Bae
    Benini, Luca
    De Micheli, Giovanni
    PROCEEDINGS OF THE 2016 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE), 2016, : 1465 - 1468
1