VLSI architecture for feedforward networks with integral back-propagation

A mixed analog/digital VLSI chip architecture is proposed which can be used to implement large (multi-chip) feedforward networks with learning. By combining feedforward and back-propagation circuitry on one chip, no intra-chip weight information needs to be exchanged, and chip-to-chip interconnection is minimized. The architecture is appropriate for a broad employs a new artificial neuron circuit which used two-quadrant MOSFET analog multipliers to construct weighted sums with programmable binary weights. The chip architecture is appropriate for a broad range of classification problems, and allows rapid learning using the merged back-propagation network.